test: add verilog/controller.v source fixture

2026-09-25 11:05:37 +08:00
parent 32ebf0ee3a
commit 0ec0406c07
1 changed files with 5 additions and 0 deletions
--- a/verilog/controller.v
+++ b/verilog/controller.v
@@ -0,0 +1,5 @@
 module controller(input clk, d, output reg q);
 always @(posedge clk) begin
  if (d) q <= 1'b1; else q <= 1'b0;
 end
 endmodule