From 0ec0406c0736d4ff1de3141662c44bc5fe09f3d3 Mon Sep 17 00:00:00 2001
From: xingchen <1098756313@qq.com>
Date: Fri, 25 Sep 2026 11:05:37 +0800
Subject: [PATCH] test: add verilog/controller.v source fixture

---
 verilog/controller.v | 5 +++++
 1 file changed, 5 insertions(+)
 create mode 100644 verilog/controller.v

diff --git a/verilog/controller.v b/verilog/controller.v
new file mode 100644
index 0000000..7234b34
--- /dev/null
+++ b/verilog/controller.v
@@ -0,0 +1,5 @@
+module controller(input clk, d, output reg q);
+always @(posedge clk) begin
+  if (d) q <= 1'b1; else q <= 1'b0;
+end
+endmodule