diff --git a/verilog/controller.v b/verilog/controller.v
new file mode 100644
index 0000000..7234b34
--- /dev/null
+++ b/verilog/controller.v
@@ -0,0 +1,5 @@
+module controller(input clk, d, output reg q);
+always @(posedge clk) begin
+  if (d) q <= 1'b1; else q <= 1'b0;
+end
+endmodule