test: add systemverilog/controller.sv source fixture

systemverilog/controller.sv

@@ -0,0 +1,5 @@
+module controller(input logic clk, d, output logic q);
+always_ff @(posedge clk) begin
+  if (d) q <= 1'b1; else q <= 1'b0;
+end
+endmodule