From 3be91cd3d6c42ed2e5dda00b65aefe2024a649ad Mon Sep 17 00:00:00 2001
From: xingchen <1098756313@qq.com>
Date: Fri, 25 Sep 2026 11:05:38 +0800
Subject: [PATCH] test: add systemverilog/controller.sv source fixture

---
 systemverilog/controller.sv | 5 +++++
 1 file changed, 5 insertions(+)
 create mode 100644 systemverilog/controller.sv

diff --git a/systemverilog/controller.sv b/systemverilog/controller.sv
new file mode 100644
index 0000000..368e4ff
--- /dev/null
+++ b/systemverilog/controller.sv
@@ -0,0 +1,5 @@
+module controller(input logic clk, d, output logic q);
+always_ff @(posedge clk) begin
+  if (d) q <= 1'b1; else q <= 1'b0;
+end
+endmodule