test: add systemverilog/controller.sv source fixture

2026-09-25 11:05:38 +08:00
parent 0ec0406c07
commit 3be91cd3d6
1 changed files with 5 additions and 0 deletions
--- a/systemverilog/controller.sv
+++ b/systemverilog/controller.sv
@@ -0,0 +1,5 @@
+module controller(input logic clk, d, output logic q);
+always_ff @(posedge clk) begin
+  if (d) q <= 1'b1; else q <= 1'b0;
+end
+endmodule