test: add vhdl/controller.vhd source fixture

vhdl/controller.vhd

@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity controller is
+  port(clk, d : in std_logic; q : out std_logic);
+end entity;
+architecture rtl of controller is
+begin
+  clocked: process(clk)
+  begin
+    if rising_edge(clk) then
+      q <= d;
+    end if;
+  end process;
+end architecture;