15 lines
286 B
VHDL
15 lines
286 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity controller is
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port(clk, d : in std_logic; q : out std_logic);
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end entity;
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architecture rtl of controller is
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begin
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clocked: process(clk)
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begin
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if rising_edge(clk) then
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q <= d;
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end if;
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end process;
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end architecture;
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