21 lines
627 B
VHDL
21 lines
627 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity majority_vote is
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port (channels : in std_logic_vector(2 downto 0);
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voted : out std_logic;
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fault_mask : out std_logic_vector(2 downto 0));
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end entity;
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architecture rtl of majority_vote is
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signal majority : std_logic;
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begin
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majority <= (channels(0) and channels(1)) or
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(channels(0) and channels(2)) or
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(channels(1) and channels(2));
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voted <= majority;
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fault_mask(0) <= channels(0) xor majority;
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fault_mask(1) <= channels(1) xor majority;
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fault_mask(2) <= channels(2) xor majority;
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end architecture;
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