library ieee;
use ieee.std_logic_1164.all;

entity majority_vote is
  port (channels : in std_logic_vector(2 downto 0);
        voted : out std_logic;
        fault_mask : out std_logic_vector(2 downto 0));
end entity;

architecture rtl of majority_vote is
  signal majority : std_logic;
begin
  majority <= (channels(0) and channels(1)) or
              (channels(0) and channels(2)) or
              (channels(1) and channels(2));
  voted <= majority;
  fault_mask(0) <= channels(0) xor majority;
  fault_mask(1) <= channels(1) xor majority;
  fault_mask(2) <= channels(2) xor majority;
end architecture;