15 lines
505 B
Verilog
15 lines
505 B
Verilog
module timeout_counter #(
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parameter WIDTH = 16,
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parameter LIMIT = 1000
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) (
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input wire clk, input wire rst_n, input wire clear,
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output reg timeout, output reg [WIDTH-1:0] count
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);
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin count <= 0; timeout <= 0; end
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else if (clear) begin count <= 0; timeout <= 0; end
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else if (count >= LIMIT) begin count <= LIMIT; timeout <= 1; end
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else begin count <= count + 1'b1; timeout <= 0; end
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end
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endmodule
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