module timeout_counter #(
    parameter WIDTH = 16,
    parameter LIMIT = 1000
) (
    input wire clk, input wire rst_n, input wire clear,
    output reg timeout, output reg [WIDTH-1:0] count
);
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin count <= 0; timeout <= 0; end
    else if (clear) begin count <= 0; timeout <= 0; end
    else if (count >= LIMIT) begin count <= LIMIT; timeout <= 1; end
    else begin count <= count + 1'b1; timeout <= 0; end
  end
endmodule