30 lines
740 B
VHDL
30 lines
740 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity sample_latch is
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port (clk, rst_n, sample_en : in std_logic;
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channels : in std_logic_vector(2 downto 0);
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sampled : out std_logic_vector(2 downto 0);
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valid : out std_logic);
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end entity;
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architecture rtl of sample_latch is
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signal held : std_logic_vector(2 downto 0) := (others => '0');
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signal seen : std_logic := '0';
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begin
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process(clk, rst_n)
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begin
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if rst_n = '0' then
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held <= (others => '0');
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seen <= '0';
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elsif rising_edge(clk) then
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if sample_en = '1' then
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held <= channels;
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seen <= '1';
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end if;
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end if;
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end process;
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sampled <= held;
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valid <= seen;
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end architecture;
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