feat: add rtl/sample_latch.vhd

rtl/sample_latch.vhd

@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity sample_latch is
+  port (clk, rst_n, sample_en : in std_logic;
+        channels : in std_logic_vector(2 downto 0);
+        sampled : out std_logic_vector(2 downto 0);
+        valid : out std_logic);
+end entity;
+
+architecture rtl of sample_latch is
+  signal held : std_logic_vector(2 downto 0) := (others => '0');
+  signal seen : std_logic := '0';
+begin
+  process(clk, rst_n)
+  begin
+    if rst_n = '0' then
+      held <= (others => '0');
+      seen <= '0';
+    elsif rising_edge(clk) then
+      if sample_en = '1' then
+        held <= channels;
+        seen <= '1';
+      end if;
+    end if;
+  end process;
+  sampled <= held;
+  valid <= seen;
+end architecture;