feat: add rtl/redundant_monitor.vhd

rtl/redundant_monitor.vhd

@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity redundant_monitor is
+  port (clk, rst_n, sample_en : in std_logic;
+        channels : in std_logic_vector(2 downto 0);
+        voted, valid, any_fault : out std_logic;
+        fault_mask : out std_logic_vector(2 downto 0));
+end entity;
+
+architecture rtl of redundant_monitor is
+  signal held, raw_mask : std_logic_vector(2 downto 0);
+  signal sample_valid : std_logic;
+begin
+  latch_unit : entity work.sample_latch
+    port map (clk, rst_n, sample_en, channels, held, sample_valid);
+  vote_unit : entity work.majority_vote
+    port map (held, voted, raw_mask);
+  filter_unit : entity work.fault_filter
+    port map (sample_valid, raw_mask, fault_mask, any_fault);
+  valid <= sample_valid;
+end architecture;