14 lines
542 B
Verilog
14 lines
542 B
Verilog
module watchdog_supervisor #(
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parameter WIDTH = 16,
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parameter LIMIT = 1000
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) (
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input wire clk, input wire rst_n, input wire heartbeat_async,
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input wire acknowledge, output wire alarm,
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output wire [WIDTH-1:0] elapsed
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);
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wire heartbeat_rise, timeout;
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heartbeat_sync sync_unit(clk, rst_n, heartbeat_async, heartbeat_rise);
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timeout_counter #(WIDTH, LIMIT) timer_unit(clk, rst_n, heartbeat_rise, timeout, elapsed);
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alarm_latch alarm_unit(clk, rst_n, timeout, heartbeat_rise, acknowledge, alarm);
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endmodule
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