12 lines
428 B
Verilog
12 lines
428 B
Verilog
module heartbeat_sync (
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input wire clk, input wire rst_n, input wire heartbeat_async,
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output wire heartbeat_rise
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);
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reg stage1, stage2, previous;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin stage1 <= 0; stage2 <= 0; previous <= 0; end
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else begin stage1 <= heartbeat_async; stage2 <= stage1; previous <= stage2; end
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end
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assign heartbeat_rise = stage2 && !previous;
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endmodule
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