16 lines
525 B
Verilog
16 lines
525 B
Verilog
module alarm_latch (
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input wire clk, input wire rst_n, input wire timeout,
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input wire heartbeat_rise, input wire acknowledge,
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output reg alarm
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);
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reg recovered;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin alarm <= 0; recovered <= 0; end
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else if (timeout && !heartbeat_rise) begin alarm <= 1; recovered <= 0; end
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else begin
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if (heartbeat_rise) recovered <= 1;
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if (acknowledge && recovered) begin alarm <= 0; recovered <= 0; end
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end
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end
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endmodule
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