module heartbeat_sync (
    input wire clk, input wire rst_n, input wire heartbeat_async,
    output wire heartbeat_rise
);
  reg stage1, stage2, previous;
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin stage1 <= 0; stage2 <= 0; previous <= 0; end
    else begin stage1 <= heartbeat_async; stage2 <= stage1; previous <= stage2; end
  end
  assign heartbeat_rise = stage2 && !previous;
endmodule