From dc4f037849687068c47604d9ad6dc9163147e942 Mon Sep 17 00:00:00 2001
From: xingchen <1098756313@qq.com>
Date: Fri, 25 Sep 2026 11:57:23 +0800
Subject: [PATCH] feat: add rtl/heartbeat_sync.v

---
 rtl/heartbeat_sync.v | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 rtl/heartbeat_sync.v

diff --git a/rtl/heartbeat_sync.v b/rtl/heartbeat_sync.v
new file mode 100644
index 0000000..c72a2fe
--- /dev/null
+++ b/rtl/heartbeat_sync.v
@@ -0,0 +1,11 @@
+module heartbeat_sync (
+    input wire clk, input wire rst_n, input wire heartbeat_async,
+    output wire heartbeat_rise
+);
+  reg stage1, stage2, previous;
+  always @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin stage1 <= 0; stage2 <= 0; previous <= 0; end
+    else begin stage1 <= heartbeat_async; stage2 <= stage1; previous <= stage2; end
+  end
+  assign heartbeat_rise = stage2 && !previous;
+endmodule