feat: add rtl/alarm_latch.v

rtl/alarm_latch.v

@@ -0,0 +1,15 @@
+module alarm_latch (
+    input wire clk, input wire rst_n, input wire timeout,
+    input wire heartbeat_rise, input wire acknowledge,
+    output reg alarm
+);
+  reg recovered;
+  always @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin alarm <= 0; recovered <= 0; end
+    else if (timeout && !heartbeat_rise) begin alarm <= 1; recovered <= 0; end
+    else begin
+      if (heartbeat_rise) recovered <= 1;
+      if (acknowledge && recovered) begin alarm <= 0; recovered <= 0; end
+    end
+  end
+endmodule