feat: add rtl/watchdog_supervisor.v

rtl/watchdog_supervisor.v

@@ -0,0 +1,13 @@
+module watchdog_supervisor #(
+    parameter WIDTH = 16,
+    parameter LIMIT = 1000
+) (
+    input wire clk, input wire rst_n, input wire heartbeat_async,
+    input wire acknowledge, output wire alarm,
+    output wire [WIDTH-1:0] elapsed
+);
+  wire heartbeat_rise, timeout;
+  heartbeat_sync sync_unit(clk, rst_n, heartbeat_async, heartbeat_rise);
+  timeout_counter #(WIDTH, LIMIT) timer_unit(clk, rst_n, heartbeat_rise, timeout, elapsed);
+  alarm_latch alarm_unit(clk, rst_n, timeout, heartbeat_rise, acknowledge, alarm);
+endmodule