12 lines
320 B
Systemverilog
12 lines
320 B
Systemverilog
module parity_accumulator (
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input logic clk, rst_n, clear, enable,
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input logic [7:0] data,
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output logic parity
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);
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) parity <= 1'b0;
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else if (clear) parity <= 1'b0;
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else if (enable) parity <= parity ^ (^data);
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end
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endmodule
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