13 lines
479 B
Systemverilog
13 lines
479 B
Systemverilog
module error_counters (
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input logic clk, rst_n, length_error, parity_error,
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output logic [15:0] length_count, parity_count
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);
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin length_count <= '0; parity_count <= '0; end
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else begin
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if (length_error && length_count != 16'hffff) length_count <= length_count + 1'b1;
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if (parity_error && parity_count != 16'hffff) parity_count <= parity_count + 1'b1;
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end
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end
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endmodule
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