module parity_accumulator (
    input logic clk, rst_n, clear, enable,
    input logic [7:0] data,
    output logic parity
);
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) parity <= 1'b0;
    else if (clear) parity <= 1'b0;
    else if (enable) parity <= parity ^ (^data);
  end
endmodule