feat: add rtl/error_counters.sv

rtl/error_counters.sv

@@ -0,0 +1,12 @@
+module error_counters (
+    input logic clk, rst_n, length_error, parity_error,
+    output logic [15:0] length_count, parity_count
+);
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin length_count <= '0; parity_count <= '0; end
+    else begin
+      if (length_error && length_count != 16'hffff) length_count <= length_count + 1'b1;
+      if (parity_error && parity_count != 16'hffff) parity_count <= parity_count + 1'b1;
+    end
+  end
+endmodule