feat: add rtl/frame_monitor.sv
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48
rtl/frame_monitor.sv
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48
rtl/frame_monitor.sv
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module frame_monitor #(
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parameter int MAX_LENGTH = 32
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) (
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input logic clk, rst_n, byte_valid,
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input logic [7:0] byte_data,
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output logic frame_valid,
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output logic [15:0] length_errors, parity_errors
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);
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import frame_types::*;
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state_t state;
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logic [7:0] length;
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logic parity, clear_parity, feed_parity;
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logic length_error, parity_error;
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assign clear_parity = byte_valid && state == WAIT_START && byte_data == START_BYTE;
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assign feed_parity = byte_valid && state == COLLECT &&
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byte_data != END_BYTE && length < MAX_LENGTH;
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parity_accumulator checksum(clk, rst_n, clear_parity, feed_parity, byte_data, parity);
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error_counters counters(clk, rst_n, length_error, parity_error, length_errors, parity_errors);
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= WAIT_START; length <= 0; frame_valid <= 0;
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length_error <= 0; parity_error <= 0;
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end else begin
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frame_valid <= 0;
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length_error <= 0; parity_error <= 0;
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if (byte_valid) begin
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case (state)
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WAIT_START: if (byte_data == START_BYTE) begin
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state <= COLLECT; length <= 0;
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end
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COLLECT: if (byte_data == END_BYTE) begin
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if (length == 0) length_error <= 1;
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else if (parity) parity_error <= 1;
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else frame_valid <= 1;
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state <= WAIT_START;
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end else if (length >= MAX_LENGTH) begin
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length_error <= 1; state <= DROP;
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end else begin length <= length + 1'b1; end
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DROP: if (byte_data == END_BYTE) state <= WAIT_START;
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default: state <= WAIT_START;
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endcase
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end
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end
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end
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endmodule
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